The present invention relates to semiconductor devices, and more particularly, to back-end-of-line (BEOL) interconnect structures.
Integrated circuits typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring typically connect the semiconductor devices from above the semiconductor portion of the substrate. Multiple levels of metal interconnect wiring above the semiconductor portion of the substrate are connected together to form a back-end-of-line (“BEOL”) interconnect structure. Within such structure, metal lines run parallel to the substrate and conductive vias run perpendicular to the substrate, the conductive vias interconnecting the different levels of metal wiring lines.
Two developments contribute to increased performance of contemporary integrated circuits. One of them is the use of copper as the interconnect metal in BEOL interconnect structures, due to the higher conductivity of copper than other traditional metals such as aluminum. Another development is the use of a low dielectric constant (“low-K”) dielectric material in interlevel dielectric (“ILD”) layers of the structure.
When copper is used as the metal in the interconnect wiring layers, a dielectric barrier layer or “cap” is typically required between copper features and the ILD layer to prevent copper from diffusing into certain types of ILD dielectric material to prevent the copper from spoiling the ILD dielectric material.
Under certain circumstances, chips may be subjected to external stresses, either during the manufacture or packaging of the chips, or when the packaged chips are mounted or installed in an electronic system for use. Occasionally, such stresses can cause cracking and delamination of dielectric and metal films therein. Difficulties lie in finding appropriate materials and manufacturing processes which permit copper metal lines to be utilized in certain types of low-K ILD materials, particularly when high stress conditions are present after UV processing.